In recent years much effort has been directed toward developing digital logic circuits which combine bipolar and CMOS technologies in a single integrated circuit. The marriage of bipolar and CMOS technologies is particularly advantageous since the superior aspects of each may be exploited and combined to yield optimal circuit performance.
For example, CMOS circuits have the advantages of extremely low quiescent power consumption, rail-to-rail output capability, high density and a very high input impedance. Bipolar logic circuits, on the other hand, are useful in driving large capacitive loads, have fast switching capabilities and feature better performance over temperature and power supply. These attributes have led to the development of a family of BiCMOS inverting logic circuits which employ bipolar transistors to drive output loads, while utilizing CMOS devices to perform the basic logic functions.
BiCMOS inverter circuits (including the closely-related category of NAND logic gate circuits) are numerous and well-known in the prior art--so much so that their use dominates most digital logic designs. This reliance is so pervasive that, for instance, the conventional way of implementing a non-inverting buffer is to connect two inverting buffers in series. In other words, non-inverting logic circuits are essentially devoid in past designs.
In general, non-inverting logic functions (e.g., OR gates) have been implemented in the past using inverting logic circuits (e.g., NOR gates) connected in series with an inverting buffer. The obvious disadvantage of such a configuration is the additional circuitry and greater complexity it requires. Furthermore, by including two logic gates between the input signal and output signal, the delay between a valid input transition and a valid output transition becomes about twice as long as the delay associated with a single stage device.
Another drawback of conventional BiCMOS logic circuitry is its need for high supply voltage during normal operation. This means that many prior art BiCMOS circuits do not operate well once the power supply voltage (e.g., V.sub.DD) drops from its normal operating range (e.g., 5 volts). This latter characteristic is of particular concern since there is a growing momentum in the semiconductor industry to lower the standard operating supply potential from 5 volts to 3 volts in order to decrease the electric field to which the devices are subjected. When such a change is actually implemented, entire categories of BiCMOS logic circuits devices would no longer be feasible for use in this low operating supply environment.
Thus, what is needed is an integrated circuit combining CMOS and bipolar technologies which implements a non-inverting buffer function in a single stage. Such a circuit should also be capable of operating at a reduced supply potential. As will be seen, the present invention provides a BiCMOS buffer stage providing both inverting and non-inverting outputs. In addition, the invented non-inverting buffer stage is capable of operation at reduced supply potentials. Adoption of the present invention promises to vastly reduce the complexity, while simultaneously increasing the speed and performance of modern digital integrated circuits fabricated using BiCMOS technology.